1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to transistors of high performance for low power applications, such as digital circuit portions and the like.
2. Description of the Related Art
Advanced integrated circuits include a large number of circuit elements on a given chip area according to a specified circuit layout, wherein transistors, such as field effect transistors, represent an important component that is used as switching element, as current and/or voltage amplifier and the like. In sophisticated applications requiring high performance, the transistors are formed in and above substantially crystalline semiconductor regions that are formed at specified substrate locations to act as active regions, that is, to act, at least temporarily, as conductive areas for creating a controlled current flow. To this end, the active regions are modified by incorporating dopant species in order to adapt the electronic characteristics, for instance by providing PN junctions. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as micro-processors, storage chips and the like, CMOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of transistors, e.g., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A transistor, irrespective of whether an N-channel transistor or a P-channel transistor or any other transistor architecture is considered, comprises PN junctions that are formed by an interface of highly doped regions, such as drain and source regions, with a lightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In the case of a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region substantially affects the performance of the MOS transistors. Thus, the scaling of the channel length, and associated therewith the reduction of channel resistivity, renders the channel length a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, entails a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the dimensions of transistors. For example, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions so as to provide low sheet and contact resistivity in combination with a desired channel controllability in order to counter so-called short channel effects, such as drain-induced barrier lowering and the like. In addition, the vertical location of the PN junctions with respect to the gate insulation layer also represents a critical design criterion in view of leakage current control, as reducing the channel length also requires reducing the depth of the drain and source regions with respect to the interface formed by the gate insulation layer and the channel region, thereby calling for sophisticated implantation techniques.
In sophisticated field effect transistors, for instance, the dopant profiles of the drain and source regions require sophisticated implantation techniques in which highly doped yet shallow profiles may be provided so as to connect to the channel region, wherein such shallow doped regions are referred to as drain and source extension regions. Furthermore, deep drain and source regions are required with a high dopant concentration and with increased lateral offset from the channel region in order to provide an appropriately shaped electrical field in transistors having an extremely short channel length. Moreover, typically counter-doped regions or halo regions have to be provided at a certain depth and at or below the channel region in order to appropriately adjust essential transistor characteristics, such as threshold voltage and the like. During the corresponding implantation processes, the gate electrode structure is used as an implantation mask, thereby ensuring the self-aligned positioning of the complex drain and source regions. To this end, the gate electrode structures typically comprise a corresponding spacer structure, whose width may be appropriately selected for the implantation process under consideration, for instance the extension and halo implantation and the implantation of the deep drain and source regions, thereby also requiring sophisticated patterning strategies in highly sophisticated semiconductor devices. That is, in current cutting-edge devices used for low power applications, i.e., for applications operated at supply voltages of approximately 10 volts and significantly less, high performance transistors may be used with a gate length of 50 nm and significantly less, such as 30 nm and less, wherein, in densely packed device areas, the lateral space between the densely packed gate electrode structures may be of similar order of magnitude. Consequently, any structural irregularities or process non-uniformities, which may be introduced during the complex process of patterning the gate electrode structures and the corresponding spacer elements, may significantly affect the resulting dopant profile. Moreover, implantation-induced damage in the active regions of the transistors typically require sophisticated anneal processes, which may be associated with a certain degree of dopant diffusion, which in turn results in dopant fluctuations and thus in significant transistor variability. Moreover, recently additional mechanisms for enhancing performance of sophisticated field effect transistors have been implemented, which aim at increasing the charge carrier mobility in the channel regions for a given channel length, thereby potentially achieving a performance improvement that is comparable with the advance to further reduced overall device dimensions, while avoiding many of the above-described problems involved with extremely small critical dimensions. For example, the lattice structure in respective semiconductor regions, such as the channel region, may be modified, for instance by creating tensile or compressive strain therein, which thus results in a modified mobility of electrons and holes, respectively. For example, creating uniaxial tensile strain in the channel region of a field effect transistor with respect to the current flow direction increases the mobility of electrons, which in turn may directly translate into a corresponding increase of transistor performance. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing performance of P-type transistors. In advanced CMOS devices, therefore, an efficient mechanism has been implemented on the basis of a highly stressed dielectric material formed above the transistors, wherein the dielectric material with high internal compressive stress is positioned above P-channel transistors and dielectric material with high internal tensile stress is positioned above N-channel transistors. This very efficient mechanism, however, becomes increasingly less effective since the reduced space between laterally adjacent gate electrode structures increasingly imposes significant restrictions to the deposition processes, which are used for forming the highly stressed dielectric material and for patterning the same.
In other strategies, a gain in performance of P-channel transistors is achieved by selectively incorporating a strain-inducing silicon/germanium alloy in the active region after patterning the gate electrode structures so that the silicon/germanium alloy induces a compressive strain in the adjacent channel region. Although generally this mechanism provides an efficient strategy for enhancing performance of P-channel transistors, lattice-induced damage in the silicon/germanium alloy and different diffusion conditions with respect to the silicon base material may also increasingly influence the finally obtained performance gain and may also affect the variability of the transistor characteristics.
Consequently, although many advanced process strategies have been implemented into the process flow for fabricating sophisticated field effect transistors for low power applications, the transistor characteristics and in particular the characteristics of the drain and source regions obtained on the basis of implantation processes and associated anneal techniques, in particular in combination with superior performance enhancing mechanisms, may no longer be compatible with a further reduction of critical dimensions of the semiconductor devices.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.